 `include "top_define.v"
module cam_top ( clk,
                 rst_n,
                 ram_dp_cfg_register,
                 ram_2p_cfg_register,
                 mac_sour,
                 port_sour,
                 // frame_length,
                 // frame_length_en,
                 // himac_broadcast_frm,
                 himac_loopback_on_off,
                 mac_dest,
                 mac_addr_en,
                 look_fail,
                 
                 broadcast_pkt_pass,
                 broadcast_pkt_ack,
                 unknow_pkt_pass,
                 unkonw_pkt_ack,    
                                   
                 busy,
                 outport,
                 outport_en,

                 //cpu\u63a5\u53e3
                 CPU_read_table_q_vld,
                 CPU_read_table_rd_en,
                 CPU_read_table_addr,
                 CPU_read_table_q,
                 CPU_write_table_wr_en,
                 CPU_write_table_data,
                 live_time_val, 
                 live_time_i,  //cpu\u63a5\u53e3
                 //bus1\u66f4\u65b0\u67e5\u627e\u8868 \u8f93\u51fa \u7528\u4e8e\u5176\u4f59\u603b\u7ebf\u603b\u7ebf\u4e2d\u7684\u603b\u7ebf\u4e00\u8868\u66f4\u65b0\uff0c\u5220\u9664
                 bus1_table_addr2,            
                 bus1_table_ram_addr_convert,                       
                 bus1_table_data2,            
                 bus1_table_ram_data_convert, 
                 bus1_table_wren2,            
                 bus1_table_ram_wr_en_convert,
                 //bus2\u66f4\u65b0\u67e5\u627e\u8868  \u8f93\u5165 \u7528\u4e8e2\uff0c3\uff0c4\u603b\u7ebf\u66f4\u65b0\uff0c\u5220\u9664
                 bus2_table_addr2,            
                 bus2_table_ram_addr_convert,                       
                 bus2_table_data2,            
                 bus2_table_ram_data_convert, 
                 bus2_table_wren2,            
                 bus2_table_ram_wr_en_convert, 
                 //bus3\u66f4\u65b0\u67e5\u627e\u8868  \u8f93\u5165 \u7528\u4e8e2\uff0c3\uff0c4\u603b\u7ebf\u66f4\u65b0\uff0c\u5220\u9664
                 bus3_table_addr2,            
                 bus3_table_ram_addr_convert,                       
                 bus3_table_data2,            
                 bus3_table_ram_data_convert, 
                 bus3_table_wren2,            
                 bus3_table_ram_wr_en_convert,
                 //bus4\u66f4\u65b0\u67e5\u627e\u8868  \u8f93\u5165 \u7528\u4e8e2\uff0c3\uff0c4\u603b\u7ebf\u66f4\u65b0\uff0c\u5220\u9664
                 bus4_table_addr2,            
                 bus4_table_ram_addr_convert,                       
                 bus4_table_data2,            
                 bus4_table_ram_data_convert, 
                 bus4_table_wren2,            
                 bus4_table_ram_wr_en_convert,                                       
                 
                 collision_detect_on_off,
                 collision_port_1,         //  mac \u5730\u5740\u51b2\u7a81\u7684\u7b2c\u4e00\u4e2a\u6e90\u7aef\u53e3\u53f7
                 collision_port_2,         //  mac \u5730\u5740\u51b2\u7a81\u7684\u7b2c\u4e8c\u4e2a\u6e90\u7aef\u53e3\u53f7
                 collision_mac_addr_1,     //  mac \u5730\u5740\u51b2\u7684\u6e90MAC\u5730\u5740\u7684\u9ad832\u4f4d
                 collision_mac_addr_2,     //  mac \u5730\u5740\u51b2\u7684\u6e90MAC\u5730\u5740\u7684\u4f4e16\u4f4d \uff0c \u6b64\u5bc4\u5b58\u5668\u7684\u6700\u4f4e\u4f4d\u8868\u793a\u662f\u5426\u6709\u51b2\u7a81
                 collision_wren      ,     //  \u51b2\u7a81\u4fe1\u606f\u7684\u5199\u4f7f\u80fd  
                 init_end            
                 // cam_every_hm_num_rden,
                 // cam_every_hm_num_address_cpu,
                 // cam_every_hm_num_cpu 
                );
input clk;
input rst_n;
input [11:0]ram_dp_cfg_register;
input [9:0]ram_2p_cfg_register;
input[47:0] mac_sour;
input[3:0] port_sour;
input[47:0] mac_dest;
// input[10:0] frame_length;
// input       frame_length_en;
// input      himac_broadcast_frm;     // \u5982\u679c himac_broadcast_frm \u7f6e 1 \uff0c\u8868\u793a\u4eceHIMAC\u7aef\u53e3\u63a5\u6536\u5230\u4e86\u4e00\u4e2aHIMAC\u5e7f\u64ad\u5e27
                                    // \u8fd9\u4e2a\u5e7f\u64ad\u5e27\u9700\u8981\u7279\u6b8a\u5904\u7406
                                    // \u5982\u679c\u53d1\u73b0\u8fd9\u4e2aHIMAC\u5e7f\u64ad\u5e27\u4e2d\u542b\u6709\u4ee5\u592a\u7f51\u5e27\u6e90MAC\u5730\u5740\u5df2\u7ecf\u5b58\u5728\u4e8e\u8f6c\u53d1\u8868\u4e2d\uff0c\u5219\u8fd9\u4e2a\u4ee5\u592a\u7f51\u5e27\u5c5e\u4e8e\u91cd\u590d\u5e27\uff0c\u9700\u8981\u4e22\u5f03
input      himac_loopback_on_off;

input      mac_addr_en;

output  look_fail;

input   broadcast_pkt_pass;
output  broadcast_pkt_ack;
input   unknow_pkt_pass;
output  unkonw_pkt_ack;

output busy;
output[3:0] outport;
output outport_en;

input live_time_val;
input [31:0] live_time_i;
//bus1\u66f4\u65b0\u53e6\u4e09\u6761\u603b\u7ebf\u4e2d\u7684\u67e5\u627e\u8868\uff08table_bus1\uff09
output reg [9:0]  bus1_table_addr2;            
output wire[9:0]  bus1_table_ram_addr_convert; 
output reg [71:0] bus1_table_data2;            
output wire[71:0] bus1_table_ram_data_convert; 
output reg        bus1_table_wren2;            
output wire       bus1_table_ram_wr_en_convert;
//bus2\u66f4\u65b0\u67e5\u627e\u8868
input [9:0]  bus2_table_addr2;//\u66f4\u65b0\u3001\u5220\u9664           
input [9:0]  bus2_table_ram_addr_convert;//CPU\u66f4\u65b0                       
input [71:0] bus2_table_data2;//\u66f4\u65b0\u3001\u5220\u9664          
input [71:0] bus2_table_ram_data_convert;//CPU\u66f4\u65b0 
input        bus2_table_wren2;//\u66f4\u65b0\u3001\u5220\u9664          
input        bus2_table_ram_wr_en_convert;//CPU\u66f4\u65b0
//bus3\u66f4\u65b0\u67e5\u627e\u8868
input [9:0]  bus3_table_addr2;//\u66f4\u65b0\u3001\u5220\u9664           
input [9:0]  bus3_table_ram_addr_convert;//CPU\u66f4\u65b0                       
input [71:0] bus3_table_data2;//\u66f4\u65b0\u3001\u5220\u9664           
input [71:0] bus3_table_ram_data_convert;//CPU\u66f4\u65b0 
input        bus3_table_wren2;//\u66f4\u65b0\u3001\u5220\u9664           
input        bus3_table_ram_wr_en_convert;//CPU\u66f4\u65b0
//bus4\u66f4\u65b0\u67e5\u627e\u8868
input [9:0]  bus4_table_addr2;//\u66f4\u65b0\u3001\u5220\u9664          
input [9:0]  bus4_table_ram_addr_convert;//CPU\u66f4\u65b0                       
input [71:0] bus4_table_data2;//\u66f4\u65b0\u3001\u5220\u9664            
input [71:0] bus4_table_ram_data_convert;//CPU\u66f4\u65b0 
input        bus4_table_wren2;//\u66f4\u65b0\u3001\u5220\u9664            
input        bus4_table_ram_wr_en_convert;//CPU\u66f4\u65b0

input           collision_detect_on_off;
output [3:0]   collision_port_1;         //  mac \u5730\u5740\u51b2\u7a81\u7684\u7b2c\u4e00\u4e2a\u6e90\u7aef\u53e3\u53f7
output [3:0]   collision_port_2;         //  mac \u5730\u5740\u51b2\u7a81\u7684\u7b2c\u4e8c\u4e2a\u6e90\u7aef\u53e3\u53f7
output [31:0]   collision_mac_addr_1;     //  mac \u5730\u5740\u51b2\u7684\u6e90MAC\u5730\u5740\u7684\u9ad832\u4f4d
output [15:0]   collision_mac_addr_2;     //  mac \u5730\u5740\u51b2\u7684\u6e90MAC\u5730\u5740\u7684\u4f4e16\u4f4d \uff0c \u6b64\u5bc4\u5b58\u5668\u7684\u6700\u4f4e\u4f4d\u8868\u793a\u662f\u5426\u6709\u51b2\u7a81
output          collision_wren;            //  \u51b2\u7a81\u4fe1\u606f\u7684\u5199\u4f7f\u80fd 
output          init_end; 

// input         cam_every_hm_num_rden;
// input[7:0]    cam_every_hm_num_address_cpu;
// output[31:0]  cam_every_hm_num_cpu;

reg [71:0] table_q1_ff              ;
reg [71:0] table_ram_q_toconvert_ff ;
reg [71:0] table_q2_ff              ;
reg [71:0] bus2_table_q2_ff         ;
reg [71:0] bus3_table_q2_ff         ;
reg [71:0] bus4_table_q2_ff         ;


(*mark_debug = "true"*)wire hash_en;
(*mark_debug = "true"*)wire study_fail;
wire [9:0]  addr_as,addr_al;
wire [9:0]  addr_b;
wire [71:0]  data_as,data_al;
wire [71:0]  data_b;
wire wren_as,wren_al;
wire wren_b;
wire [71:0]  q_as,q_al;
wire q_as_en,q_al_en;
wire [71:0]  q_b;
wire [12:0] time_now;
wire studying,looking,look_rden,look_update;
wire initing_study;
wire initing_lookup;
(*mark_debug = "true"*)wire studying1;
(*mark_debug = "true"*)wire looking1;
(*mark_debug = "true"*)wire [9:0]hash_dest;
(*mark_debug = "true"*)wire [9:0]hash_sour;

wire [9:0] table_addr1,table_addr2;
wire [71:0] table_data1,table_data2;
wire table_wren1,table_wren2;
wire [71:0] table_q1,table_q2;
wire [71:0] bus2_table_q2;
wire [71:0] bus3_table_q2;
wire [71:0] bus4_table_q2;
wire [71:0] bus2_lookup_q,bus3_lookup_q,bus4_lookup_q;

wire [82:0]  bus2_fifo_data_i;
wire [82:0]  bus3_fifo_data_i;
wire [82:0]  bus4_fifo_data_i;

wire [82:0]  bus2_fifo_data_o;
wire [82:0]  bus3_fifo_data_o;
wire [82:0]  bus4_fifo_data_o;

reg  [82:0]  bus2_fifo_data_o_ff;
reg  [82:0]  bus3_fifo_data_o_ff;
reg  [82:0]  bus4_fifo_data_o_ff;

wire [9:0]   bus2_table_addr_o;
wire         bus2_table_wren_o;
wire [71:0]  bus2_table_data_o;
wire [9:0]   bus3_table_addr_o;
wire         bus3_table_wren_o;
wire [71:0]  bus3_table_data_o;
wire [9:0]   bus4_table_addr_o;
wire         bus4_table_wren_o;
wire [71:0]  bus4_table_data_o;

(*mark_debug = "true"*)wire bus2_empty      ;
(*mark_debug = "true"*)wire bus2_almost_full;
wire bus3_empty      ;
wire bus3_almost_full;
wire bus4_empty      ;
wire bus4_almost_full;

(*mark_debug = "true"*)wire bus2_table_wren;
(*mark_debug = "true"*)wire bus2_table_rden;
wire bus3_table_wren;
wire bus3_table_rden;
wire bus4_table_wren;
wire bus4_table_rden;

output CPU_read_table_q_vld;
input CPU_read_table_rd_en;
input [11:0] CPU_read_table_addr;
output [31:0] CPU_read_table_q;
wire  [71:0] table_ram_data_convert;
wire table_ram_wr_en_convert;  
input CPU_write_table_wr_en;
input [31:0] CPU_write_table_data;
                              
wire [9:0] table_ram_addr_convert;
wire  [71:0] table_ram_q_toconvert;

wire                  broadcast_pkt_ack;
wire                  unkonw_pkt_ack;

wire collision_detect_on_off;
wire [3:0] collision_port_1;         //  mac \u5730\u5740\u51b2\u7a81\u7684\u7b2c\u4e00\u4e2a\u6e90\u7aef\u53e3\u53f7
wire [3:0] collision_port_2;         //  mac \u5730\u5740\u51b2\u7a81\u7684\u7b2c\u4e8c\u4e2a\u6e90\u7aef\u53e3\u53f7
wire [31:0] collision_mac_addr_1;     //  mac \u5730\u5740\u51b2\u7684\u6e90MAC\u5730\u5740\u7684\u9ad832\u4f4d
wire [15:0] collision_mac_addr_2;     //  mac \u5730\u5740\u51b2\u7684\u6e90MAC\u5730\u5740\u7684\u4f4e16\u4f4d \uff0c \u6b64\u5bc4\u5b58\u5668\u7684\u6700\u4f4e\u4f4d\u8868\u793a\u662f\u5426\u6709\u51b2\u7a81
wire collision_wren;            //  \u51b2\u7a81\u4fe1\u606f\u7684\u5199\u4f7f\u80fd
wire init_end0,init_end1;//test
wire study_busy,lookup_busy;
study     study_inst( .clk(clk),
                      .rst_n(rst_n),
                      
                      .mac_sour(mac_sour),
                      .port_sour(port_sour),
                      // .himac_broadcast_frm(himac_broadcast_frm),
                      .himac_loopback_on_off(himac_loopback_on_off),
                      .hash_en(hash_en),
                      .hash_sour(hash_sour),

                      .study_fail(study_fail),

                      .busy(study_busy),

                      .mac_addr_en(mac_addr_en),
                      .addr_a(addr_as),
                      .data_a(data_as),
                      .wren_a(wren_as),
                      .q_as(q_as),
                      .q_as_en(q_as_en),
                      .time_now(time_now),
                      .studying(studying),
                      .studying1(studying1),
                      .initing(initing_study),

                      .collision_detect_on_off(collision_detect_on_off),
                      .collision_port_1(collision_port_1),              //  mac \u5730\u5740\u51b2\u7a81\u7684\u7b2c\u4e00\u4e2a\u6e90\u7aef\u53e3\u53f7
                      .collision_port_2(collision_port_2),              //  mac \u5730\u5740\u51b2\u7a81\u7684\u7b2c\u4e8c\u4e2a\u6e90\u7aef\u53e3\u53f7
                      .collision_mac_addr_1(collision_mac_addr_1),      //  mac \u5730\u5740\u51b2\u7684\u6e90MAC\u5730\u5740\u7684\u9ad832\u4f4d
                      .collision_mac_addr_2(collision_mac_addr_2),      //  mac \u5730\u5740\u51b2\u7684\u6e90MAC\u5730\u5740\u7684\u4f4e16\u4f4d \uff0c \u6b64\u5bc4\u5b58\u5668\u7684\u6700\u4f4e\u4f4d\u8868\u793a\u662f\u5426\u6709\u51b2\u7a81
                      .collision_wren(collision_wren)  ,                 //  \u51b2\u7a81\u4fe1\u606f\u7684\u5199\u4f7f\u80fd

                      .is_Nstudy_en(live_time_i[30]),
                      .init_end(init_end0)//test
                     );
lookup_cam   lookupcam_inst( .clk(clk),
                             .rst_n(rst_n),
                             
                             // .himac_broadcast_frm(himac_broadcast_frm),
                             // .himac_loopback_on_off(himac_loopback_on_off),
                             .mac_dest(mac_dest),
                             .hash_en(hash_en),
                             .hash_dest(hash_dest),
                             .hash_sour(hash_sour),
                             .mac_sour(mac_sour),
                             .port_sour(port_sour),
                             .time_now(time_now),
                             .look_fail(look_fail),
       
                             .broadcast_pkt_pass(broadcast_pkt_pass),
                             .broadcast_pkt_ack(broadcast_pkt_ack),
                             .unknow_pkt_pass(unknow_pkt_pass),
                             .unkonw_pkt_ack(unkonw_pkt_ack),
       
                             .busy(lookup_busy),
                             .outport(outport),
                             .outport_en(outport_en),
       
                             .mac_addr_en(mac_addr_en),
                             .addr_a(addr_al),
                             .data_a(data_al),
                             .wren_a(wren_al),
                             .q_al(q_al),//bus1
                             .q_al_en(q_al_en),//bus1
                             .bus2_lookup_q(bus2_lookup_q),//bus2
                             .bus3_lookup_q(bus3_lookup_q),//bus3
                             .bus4_lookup_q(bus4_lookup_q),//bus4

                             .study_fail(study_fail),

                             .looking(looking),
                             .looking1(looking1),
                             .initing(initing_lookup),
                             .look_rden(look_rden),
                             .look_update(look_update),
                             .init_end(init_end1)//test
                            );
assign busy = lookup_busy | study_busy;
assign init_end = init_end0 & init_end1;
//\u5220\u9664\u5c31\u662f\u5199\u5165\u51680\u7684\u6570\u636e 
//\u5b66\u4e60\u6216\u8005\u5220\u9664\u90fd\u9700\u8981\u5199\u5165\u6570\u636e
//\u53cc\u7aef\u53e3RAM\uff0c\u4e24\u5957\u5730\u5740\u7ebf\u53ef\u8bfb\u53ef\u5199  
//\u4e24\u5957\u5730\u5740\u8868\uff1a1\u7528\u6765\u66f4\u65b0\u548c\u5b66\u4e60 
//\u6bcf\u4e2a\u5730\u5740\u8868\u6709\u4e24\u5957\u5730\u5740,\u4e00\u5957\u7528\u4e8eCPU\u7684\u8bfb\u5199\u63a7\u5236\uff0c\u4e00\u5957\u7528\u4e8e\u66f4\u65b0\u548c\u5b66\u4e60            
`ifdef ASIC
ram_dp_d1024_w72_wrapper at1_inst_asic(
    .clka(clk),
    .clkb(clk),
    .ram_dp_cfg_register(ram_dp_cfg_register),
    .wea(table_wren1),
    .web(table_ram_wr_en_convert),
    .addra(table_addr1),
    .addrb(table_ram_addr_convert),
    .dina(table_data1),
    .dinb(table_ram_data_convert),
    .douta(table_q1),
    .doutb(table_ram_q_toconvert)
);
ram_dp_d1024_w72_wrapper at2_inst_asic(
    .clka(clk),
    .clkb(clk),
    .ram_dp_cfg_register(ram_dp_cfg_register),
    .wea(table_wren2),
    .web(table_ram_wr_en_convert),
    .addra(table_addr2),
    .addrb(table_ram_addr_convert),
    .dina(table_data2),
    .dinb(table_ram_data_convert),
    .douta(table_q2),
    .doutb()
);
`else           
TDP_RAM_W72_D1024 U_study(
    .addra(table_addr1),
    .addrb(table_ram_addr_convert),
    .clka(clk),
    .clkb(clk),
    .dina(table_data1),
    .dinb(table_ram_data_convert),
    .wea(table_wren1),
    .web(table_ram_wr_en_convert),
    .douta(table_q1             ),
    .doutb(table_ram_q_toconvert)
    );
//2\u7528\u6765\u5220\u9664\u548c\u67e5\u627e\uff0c\u67e5\u627e\u9700\u8981\u540c\u6b65\u5b66\u4e60\u5730\u5740\u8868\u7684\u6570\u636eRAM
//*********************************************
//                 bus1
//*********************************************
TDP_RAM_W72_D1024 U_lookup1(
    .addra     (table_addr2                ),//\u67e5\u627e\u5730\u5740,\u5220\u9664\u5730\u5740//\u66f4\u65b0\u5730\u5740
    .addrb     (table_ram_addr_convert     ),
    .clka      (clk                        ),
    .clkb      (clk                        ),
    .dina      (table_data2                ),
    .dinb      (table_ram_data_convert     ),
    .wea       (table_wren2                ),
    .web       (table_ram_wr_en_convert    ),
    .douta     (table_q2                   ),//lookup table out
    .doutb     (                           )
    );
`endif
//*********************************************
//                 bus2
//*********************************************
assign bus2_fifo_data_i = {bus2_table_wren2,bus2_table_addr2,bus2_table_data2};
assign bus2_table_wren  = bus2_table_wren2 & (~bus2_almost_full);//\u975e\u6ee1 \u5199
assign bus2_table_rden  = look_rden & (~bus2_empty);//\u975e\u7a7a \u8bfb
table_data_W_83_D_256_FIFO U_bus2_table_data_W_83_D_256_FIFOmodule (   
    .clock        (clk             ),
    .rst_n        (rst_n           ),
    .ram_2p_cfg_register(ram_2p_cfg_register),
    .fifo_wen     (bus2_table_wren ),
    .fifo_wdata   (bus2_fifo_data_i),
    .fifo_ren     (bus2_table_rden ),
    .fifo_rdata   (bus2_fifo_data_o),
    .fifo_empty_rd(bus2_empty      ),
    .almost_full  (bus2_almost_full)
    ); 
`ifdef ASIC
ram_dp_d1024_w72_wrapper U_lookup2_asic(
    .clka(clk),
    .clkb(clk),
    .ram_dp_cfg_register(ram_dp_cfg_register),
    .wea(bus2_table_wren_o),
    .web(bus2_table_ram_wr_en_convert),
    .addra(bus2_table_addr_o),
    .addrb(bus2_table_ram_addr_convert),
    .dina(bus2_table_data_o),
    .dinb(bus2_table_ram_data_convert),
    .douta(bus2_table_q2),
    .doutb()
);
`else
TDP_RAM_W72_D1024 U_lookup2(
    .addra     (bus2_table_addr_o                 ),//\u6b64\u5904\u8981\u8003\u8651\u67e5\u627e\u5730\u5740\u6765\u81ea\u6b21\u603b\u7ebf\u54c8\u5e0c\u6620\u5c04\uff0c\u5220\u9664\u5730\u5740\u6765\u81ea\u5176\u4ed6\u603b\u7ebf\u5728MUX\u6a21\u5757\u533a\u5206
    .addrb     (bus2_table_ram_addr_convert ),
    .clka      (clk                         ),
    .clkb      (clk                         ),
    .dina      (bus2_table_data_o            ),
    .dinb      (bus2_table_ram_data_convert ),
    .wea       (bus2_table_wren_o            ),
    .web       (bus2_table_ram_wr_en_convert),
    .douta     (bus2_table_q2               ),
    .doutb     (                            )
    );
`endif
//*********************************************
//                 bus3
//*********************************************
assign bus3_fifo_data_i = {bus3_table_wren2,bus3_table_addr2,bus3_table_data2};
assign bus3_table_wren  = bus3_table_wren2 & (~bus3_almost_full);
assign bus3_table_rden  = look_rden & (~bus3_empty);
table_data_W_83_D_256_FIFO U_bus3_table_data_W_83_D_256_FIFOmodule (   
    .clock        (clk             ),
    .rst_n        (rst_n           ),
    .ram_2p_cfg_register(ram_2p_cfg_register),
    .fifo_wen     (bus3_table_wren ),
    .fifo_wdata   (bus3_fifo_data_i),
    .fifo_ren     (bus3_table_rden ),
    .fifo_rdata   (bus3_fifo_data_o),
    .fifo_empty_rd(bus3_empty      ),
    .almost_full  (bus3_almost_full)
    ); 
`ifdef ASIC
ram_dp_d1024_w72_wrapper U_lookup3_asic(
    .clka(clk),
    .clkb(clk),
    .ram_dp_cfg_register(ram_dp_cfg_register),
    .wea(bus3_table_wren_o),
    .web(bus3_table_ram_wr_en_convert),
    .addra(bus3_table_addr_o),
    .addrb(bus3_table_ram_addr_convert),
    .dina(bus3_table_data_o),
    .dinb(bus3_table_ram_data_convert),
    .douta(bus3_table_q2),
    .doutb()
);
`else
TDP_RAM_W72_D1024 U_lookup3(
    .addra     (bus3_table_addr_o                 ),
    .addrb     (bus3_table_ram_addr_convert ),
    .clka      (clk                         ),
    .clkb      (clk                         ),
    .dina      (bus3_table_data_o            ),
    .dinb      (bus3_table_ram_data_convert ),
    .wea       (bus3_table_wren_o            ),
    .web       (bus3_table_ram_wr_en_convert),
    .douta     (bus3_table_q2               ),
    .doutb     (                            )
    );
`endif
//*********************************************
//                  bus4
//*********************************************
assign bus4_fifo_data_i = {bus4_table_wren2,bus4_table_addr2,bus4_table_data2};
assign bus4_table_wren  = bus4_table_wren2 & (~bus4_almost_full);
assign bus4_table_rden  = look_rden & (~bus4_empty);
table_data_W_83_D_256_FIFO U_bus4_table_data_W_83_D_256_FIFOmodule (   
    .clock        (clk             ),
    .rst_n        (rst_n           ),
    .ram_2p_cfg_register(ram_2p_cfg_register),
    .fifo_wen     (bus4_table_wren ),
    .fifo_wdata   (bus4_fifo_data_i),
    .fifo_ren     (bus4_table_rden ),
    .fifo_rdata   (bus4_fifo_data_o),
    .fifo_empty_rd(bus4_empty      ),
    .almost_full  (bus4_almost_full)
    ); 
`ifdef ASIC
ram_dp_d1024_w72_wrapper U_lookup4_asic(
    .clka(clk),
    .clkb(clk),
    .ram_dp_cfg_register(ram_dp_cfg_register),
    .wea(bus4_table_wren_o),
    .web(bus4_table_ram_wr_en_convert),
    .addra(bus4_table_addr_o),
    .addrb(bus4_table_ram_addr_convert),
    .dina(bus4_table_data_o),
    .dinb(bus4_table_ram_data_convert),
    .douta(bus4_table_q2),
    .doutb()
);
`else
TDP_RAM_W72_D1024 U_lookup4(
    .addra     (bus4_table_addr_o           ),
    .addrb     (bus4_table_ram_addr_convert ),
    .clka      (clk                         ),
    .clkb      (clk                         ),
    .dina      (bus4_table_data_o           ),
    .dinb      (bus4_table_ram_data_convert ),
    .wea       (bus4_table_wren_o           ),
    .web       (bus4_table_ram_wr_en_convert),
    .douta     (bus4_table_q2               ),
    .doutb     (                            )
    );
`endif
//\u66f4\u6539addr_table\u4e2d\u7684\u8868\u9879   
table_ram_addr_convert  table_ram_addr_convert_U(
                              .clk(clk),
                              .rst_n(rst_n),
                              .CPU_read_table_q_vld(CPU_read_table_q_vld),
                              .CPU_read_table_addr(CPU_read_table_addr),
                              .CPU_read_table_rd_en(CPU_read_table_rd_en),
                              .CPU_read_table_q(CPU_read_table_q),
                              .CPU_write_table_wr_en(CPU_write_table_wr_en),
                              .CPU_write_table_data(CPU_write_table_data),
                              
                              .table_ram_addr_convert(table_ram_addr_convert),
                              .table_ram_data_convert(table_ram_data_convert),
                              .table_ram_wr_en_convert(table_ram_wr_en_convert),
                              .table_ram_q_toconvert(table_ram_q_toconvert_ff)  
                              );

delete dl_inst( .clk(clk),
                .rst_n(rst_n),
                
                .addr_b(addr_b),
                .data_b(data_b),
                .wren_b(wren_b),
                .q_b(q_b),
                
                .time_now(time_now),
                .studying(studying),
                .live_time_val(live_time_val),
                .live_time_i(live_time_i)
               );
               
//\u5730\u5740\u8868\u7684\u8f93\u5165\u4e8c\u9009\u4e00\uff0c\u5b66\u4e60\u72b6\u6001\u4e0b\u8f93\u51fa\u5b66\u4e60\u5730\u5740\u548c\u6570\u636e\uff0c\u5220\u9664\u72b6\u6001\u4e0b\u8f93\u51fa\u5220\u9664\u5730\u5740\u548c\u6570\u636e
addr_table_mux addr_table_mux_U1(
               .clk  (clk  ),
               .rst_n(rst_n),
               .studying(studying),
               .studying1(studying1),
               .initing(initing_study),
               //\u8f93\u5165\u7aef\u53e3
               .delete_addr(addr_b),
               .delete_data(data_b),
               .delete_wren(wren_b),
               .delete_q(q_b),//\u7528\u6765\u5224\u5b9a\u8001\u5316\u65f6\u95f4
                 
               .study_addr(addr_as),
               .study_data(data_as),
               .study_wren(wren_as),
               .study_q(q_as),
               .q_as_en(q_as_en),
               //\u8f93\u51fa\u7aef\u53e3
               .table_addr(table_addr1),
               .table_data(table_data1),
               .table_wren(table_wren1),
               //in
               .table_q(table_q1_ff)
                );
//\u67e5\u627e
look_addr_table_mux look_addr_table_mux_U2(
               .clk  (clk  ),
               .rst_n(rst_n),
               .looking(looking),
               .looking1(looking1),
               .initing(initing_lookup),
               .look_update(look_update),
               //in  
               .look_addr(addr_al),//\u67e5\u627e\uff0c\u66f4\u65b0
               .look_data(data_al),//\u67e5\u627e\uff0c\u66f4\u65b0
               .look_wren(wren_al),//\u67e5\u627e\uff0c\u66f4\u65b0
               //in \u5220\u9664
               .delete_addr(addr_b),
               .delete_data(data_b),
               .delete_wren(wren_b),
               //
               .bus2_fifo_data(bus2_fifo_data_o_ff),
               .bus3_fifo_data(bus3_fifo_data_o_ff),
               .bus4_fifo_data(bus4_fifo_data_o_ff),
               //out
               .q_al_en      (q_al_en),
               .bus1_lookup_q(q_al),//lookup bus1 out 
               .bus2_lookup_q(bus2_lookup_q),//lookup bus2 out 
               .bus3_lookup_q(bus3_lookup_q),//lookup bus3 out 
               .bus4_lookup_q(bus4_lookup_q),//lookup bus4 out 
               //\u8f93\u51fa\u7aef\u53e3
               .bus1_table_addr(table_addr2),
               .bus1_table_data(table_data2),
               .bus1_table_wren(table_wren2),
               .bus2_table_addr(bus2_table_addr_o),
               .bus2_table_wren(bus2_table_wren_o),
               .bus2_table_data(bus2_table_data_o),
               .bus3_table_addr(bus3_table_addr_o),
               .bus3_table_wren(bus3_table_wren_o),
               .bus3_table_data(bus3_table_data_o),
               .bus4_table_addr(bus4_table_addr_o),
               .bus4_table_wren(bus4_table_wren_o),
               .bus4_table_data(bus4_table_data_o),

               .bus1_table_q (table_q2_ff     ),//lookup bus1 in
               .bus2_table_q (bus2_table_q2_ff),//lookup bus2 in
               .bus3_table_q (bus3_table_q2_ff),//lookup bus3 in
               .bus4_table_q (bus4_table_q2_ff) //lookup bus4 in
                );

hash hash_inst(
                .clk(clk),
                .rst_n(rst_n),
                .mac_dest(mac_dest),
                .mac_sour(mac_sour),
                .hash_en (hash_en),
                .mac_addr_en(mac_addr_en),
                .hash_dest(hash_dest),
                .hash_sour(hash_sour)       

);
         
assign bus1_table_ram_addr_convert        =  table_ram_addr_convert      ;          
assign bus1_table_ram_data_convert        =  table_ram_data_convert      ;         
assign bus1_table_ram_wr_en_convert       =  table_ram_wr_en_convert     ; 
//output 234\u603b\u7ebf\u4e2d\u7684table1\u66f4\u65b0\u548c\u5220\u9664
always@(posedge clk or negedge rst_n)
begin
    if(~rst_n)begin
            bus1_table_addr2 <= 'b0;
            bus1_table_data2 <= 'b0;
            bus1_table_wren2 <= 'b0;
    end
    else if(wren_al && (~initing_lookup)) begin//updata !initing
            bus1_table_addr2 <= addr_al;
            bus1_table_data2 <= data_al;
            bus1_table_wren2 <= wren_al;
    end
    else if(wren_b) begin//delete
            bus1_table_addr2 <= addr_b;
            bus1_table_data2 <= data_b;
            bus1_table_wren2 <= wren_b;
    end
    else  begin
            bus1_table_addr2 <= 'b0;
            bus1_table_data2 <= 'b0;
            bus1_table_wren2 <= 'b0;
    end
end
//////////////////////////////////////////
//SRAM \u8f93\u51fa\u6253\u4e00\u62cd
always@(posedge clk or negedge rst_n)
begin
    if(~rst_n)begin
            table_q1_ff              <= 'b0;//study
            table_ram_q_toconvert_ff <= 'b0;//study
            table_q2_ff              <= 'b0;//lookup bus1
            bus2_table_q2_ff         <= 'b0;//lookup bus2
            bus3_table_q2_ff         <= 'b0;//lookup bus3
            bus4_table_q2_ff         <= 'b0;//lookup bus4
    end
    else  begin
            table_q1_ff              <= table_q1              ;
            table_ram_q_toconvert_ff <= table_ram_q_toconvert ;
            table_q2_ff              <= table_q2              ;
            bus2_table_q2_ff         <= bus2_table_q2         ;
            bus3_table_q2_ff         <= bus3_table_q2         ;
            bus4_table_q2_ff         <= bus4_table_q2         ;
    end
end
//FIFO SRAM 输出打一拍
reg bus2_table_rden_ff ;
reg bus3_table_rden_ff ;
reg bus4_table_rden_ff ;
always@(posedge clk or negedge rst_n)
begin
    if(~rst_n)begin
           bus2_table_rden_ff <= 0;//lookup bus2
           bus3_table_rden_ff <= 0;//lookup bus3
           bus4_table_rden_ff <= 0;//lookup bus4
    end
    else  begin
           bus2_table_rden_ff <= bus2_table_rden;//lookup bus2
           bus3_table_rden_ff <= bus3_table_rden;//lookup bus3
           bus4_table_rden_ff <= bus4_table_rden;//lookup bus4
    end
end
always@(posedge clk or negedge rst_n)
begin
    if(~rst_n)begin
           bus2_fifo_data_o_ff <= 'b0;//lookup bus2
    end
    else if(bus2_table_rden_ff) begin
           bus2_fifo_data_o_ff <= bus2_fifo_data_o;
    end
    else begin
	   bus2_fifo_data_o_ff <= bus2_fifo_data_o_ff;
    end
end
always@(posedge clk or negedge rst_n)
begin
    if(~rst_n)begin
           bus3_fifo_data_o_ff <= 'b0;//lookup bus3
    end
    else if(bus3_table_rden_ff) begin
           bus3_fifo_data_o_ff <= bus3_fifo_data_o;
    end
    else begin
	   bus3_fifo_data_o_ff <= bus3_fifo_data_o_ff;
    end
end
always@(posedge clk or negedge rst_n)
begin
    if(~rst_n)begin
           bus4_fifo_data_o_ff <= 'b0;//lookup bus4
    end
    else if(bus4_table_rden_ff) begin
           bus4_fifo_data_o_ff <= bus4_fifo_data_o;
    end
    else begin
           bus4_fifo_data_o_ff <= bus4_fifo_data_o_ff;
    end
end

/*reg [6:0] outport_r;
reg       outport_en_r1;
reg       outport_en_r2;
reg       init_end_r1;
reg       init_end_r2;
reg       init_end_r3;
reg       init_end_r4;
always@(posedge clk or negedge rst_n)
begin
    if(~rst_n)
        begin
            init_end_r1<=1'b0;
            init_end_r2<=1'b0;
            init_end_r3<=1'b0;
            init_end_r4<=1'b0;
        end
    else
        begin
            init_end_r1<=init_end;
            init_end_r2<=init_end_r1;
            init_end_r3<=init_end_r2;
            init_end_r4<=init_end_r3;
        end
end

always@(posedge clk or negedge rst_n)
begin
    if(~rst_n)
        outport_r <=7'd0;
    else if(init_end==1'b0)
        outport_r <= outport_r + 1'b1;
    else if(outport== 8'hff && outport_en)
        outport_r <= 7'd65;
    else if(outport_en)
        outport_r <= outport[6:0];
    else
        outport_r <= outport_r;
end

reg [31:0] cam_every_hm_num;
reg cam_every_hm_num_wren;
wire [31:0]cam_every_hm_num_Q;
always@(posedge clk or negedge rst_n)
begin
    if(~rst_n)
    begin
        cam_every_hm_num<=32'h0;
        cam_every_hm_num_wren<=1'b0;
    end
    else if(init_end==1'b0)
    begin
    cam_every_hm_num<=32'h0;
    cam_every_hm_num_wren<=1'b1;
    end
    else if(frame_length_en && init_end_r4)
    begin
    cam_every_hm_num <=cam_every_hm_num_Q+ frame_length;
    cam_every_hm_num_wren<=1'b1;
    end
    else
    begin
    cam_every_hm_num<=cam_every_hm_num;
    cam_every_hm_num_wren<=1'b0;
    end
end
wire [31:0] cam_every_hm_num_reg;
assign  cam_every_hm_num_cpu = (cam_every_hm_num_reg[5:0] == 6'b0)? {6'b0,cam_every_hm_num_reg[31:6]}:{6'b0,(cam_every_hm_num_reg[31:6] + 26'b1)};

//\u6bcf\u4e2a\u961f\u5217\u4e2d\u7684\u6240\u6709\u5e27\u957f\u5ea6
queueFrameNumMemory U_cam_output_num(
    .addra(outport_r),
    .addrb(cam_every_hm_num_address_cpu[6:0]),
    .clka(clk),
    .clkb(clk),
    .dina(cam_every_hm_num),
    .dinb(32'b0),
    .wea(cam_every_hm_num_wren),
    .web(1'b0),
    .douta(cam_every_hm_num_Q),
    .doutb(cam_every_hm_num_reg)
    );*/
endmodule

